The present invention generally relates to a method for manufacturing a semiconductor device, and more specifically, to a technology of etching a semiconductor substrate with a first recess gate for defining a recess gate region as a mask in formation of a recess gate, thereby preventing generation of a height difference from the semiconductor substrate because a device separating film except the recess gate region is etched due to an etching selectivity.
As a channel length of a cell transistor is decreased, an ion concentration of a cell channel is increased to adjust a threshold voltage of the cell transistor. As a result, an electric field of source/drain regions is increased and leakage current is increased so that a refresh characteristic of a DRAM is degraded.
FIG. 1 is a layout diagram illustrating a conventional semiconductor device to increase the channel length of the cell transistor.
The conventional semiconductor device of FIG. 1 includes an active region 1, a recess gate region 2 and a gate region 3.
The linewidth of the recess gate region 2 is shown to be narrower by 2D than that of the gate region 3. The width between the gate regions 3 is shown to be F.
FIGS. 2a through 2f are diagrams illustrating a conventional process for manufacturing a semiconductor device. FIGS. 2a(i) through 2f(i) are cross-sectional diagrams taken along the line I-I′ of FIG. 1, and FIGS. 2a(ii) through 2f(ii) are cross-sectional diagrams taken along the line II-II′ of FIG. 1.
A device separating film 50 is formed over a semiconductor substrate 10 including a pad oxide film 13 and a pad nitride film 15.
After the pad nitride film 15 is removed, ions are implanted into the resulting structure to form well and channel ion-implanting regions (not shown). Then, a polysilicon layer 45 is formed over the resulting structure.
The polysilicon layer 45 and the pad oxide film 13 are etched with the first gate mask (not shown) which defines a recess gate region as an etching mask to form a polysilicon pattern 45 and a pad oxide pattern 13a which define the recess gate region 2 of FIG. 1.
The semiconductor substrate 10 of the recess gate region 2 of FIG. 1 is etched at a predetermined thickness to form a recess 53. Here, the polysilicon pattern 45a is simultaneously removed when the recess 53 is formed. The semiconductor substrate 10 adjacent to the device separating film 50 has a relatively slower etching speed to cause a silicon horn.
A gate insulating film 60 is formed over the exposed semiconductor substrate 10. Then, a gate conductive layer 65 for filling the recess 53 is formed, and a hard mask layer 90 is formed thereon. The gate conductive layer 65 has a deposition structure including a bottom electrode 70 and a top electrode 80.
The hard mask layer 90 and the gate conductive layer 65 are patterned with a second gate mask (not shown) for defining a gate as an etching mask to form a gate 99.
A thickness difference of bottom electrodes over the gate insulating film 60 and the device separating film makes the surface of the device separating film 50 lower than that of the silicon substrate, and causes the bottom electrode 75 of the gate formed over the silicon substrate which is an active region to be over-etched in order to etch the thick bottom electrode of the device separating film. Also, the conventional method for manufacturing a semiconductor device increases word line capacitance after the gate is formed, and degrades the operating speed of the DRAM and a refresh characteristic of the semiconductor device resulting from increase of leakage current.